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參數(shù)資料
| 型號： | PCF21132 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LCD controller/driver(LCD控制器/驅(qū)動器) |
| 中文描述： | LCD控制器/驅(qū)動器（液晶顯示控制器/驅(qū)動器） |
| 文件頁數(shù)： | 9/60頁 |
| 文件大小： | 392K |
| 代理商： | PCF21132 |
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1997 Apr 04
9
Philips Semiconductors
Product specification
LCD controller/driver
PCF2113x
8.7
Power-down mode
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no bias
level generation, all LCD-outputs are internally connected
to V
SS
) when PD = logic 1.
During power-down, the whole chip is reset and will restart
with a clear display after power-down. Therefore, the
whole chip has to be initialized after a power-down as after
initial power- up.
The device should be put into ‘display off’ mode
(instruction ‘Display control’) before putting the chip in
power-down mode, otherwise the LCD output voltages are
not defined.
8.8
Registers
The PCF2113x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘Display clear’ and ‘Cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM). The instruction
register can be written from but not read by the system
controller. The data register temporarily stores data to be
read from the DDRAM and CGRAM. When reading, data
from the DDRAM or CGRAM corresponding to the address
in the instruction register is written to the data register prior
to being read by the ‘Read data’ instruction.
8.9
Busy Flag
The Busy Flag indicates the free/busy status of the
PCF2113x. Logic 1 indicates that the chip is busy and
further instructions will not be accepted. The Busy Flag is
output to pin DB7 when RS = logic 0 and R/W = logic 1.
Instructions should only be written after checking that the
Busy Flag is logic 0 or waiting for the required number of
cycles.
8.10
Address Counter (AC)
The Address Counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
instructions ‘Set CGRAM address’ and
‘Set DDRAM address’. After a read/write operation the
Address Counter is automatically incremented or
decremented by 1. The Address Counter contents are
output to the bus (DB6 to DB0) when RS = logic 0 and
R/W = logic 1.
8.11
Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic DDRAM-to-display
mapping is shown in Fig.3. With no display shift the
characters represented by the codes in the first 24 RAM
locations starting at address 00 in line 1 are displayed.
Figures 4 and 5 show the display mapping for right and left
shift respectively.
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap- around operations for the
various modes are shown in Table 3.
Table 3
Address space and wrap-around operation
8.12
Character Generator ROM (CGROM)
The Character Generator ROM (CGROM) generates
240 character patterns in 5
×
8 dot format from 8-bit
character codes. Figures 7, 8 and 9 show the character
sets that are currently implemented.
8.13
Character Generator RAM (CGRAM)
Up to 16 user defined characters may be stored in the
Character Generator RAM (CGRAM). Some CGRAM
characters (see Fig.17) are also used to drive icons (6 if
icons blink and both icon rows are used in application; 3 if
no blink but both icon rows are used in application; 0 if no
icons are driven by the icon rows). The CGROM and
CGRAM use a common address space, of which the first
column is reserved for the CGRAM (see Fig.7). Figure 10
shows the addressing principle for the CGRAM.
MODE
1
×
24
00 to 4F
4F to 00
2
×
12
address space
read/write wrap-around
(moves to next line)
display shift wrap-around
(stays within line)
00 to 27; 40 to 67
27 to 40; 67 to 00
4F to 00
27 to 00; 67 to 40
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF211410 | LCD controller/drivers(LCD控制器/驅(qū)動器) |
| PCF2116AHZ | JT 66C 66#22D PIN RECP |
| PCF2116CHZ | LCD controller/drivers |
| PCF211412 | LCD controller/drivers(LCD控制器/驅(qū)動器) |
| PCF2114xU | LCD controller/drivers(LCD控制器/驅(qū)動器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF2113A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controller/driver |
| PCF2113AH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| PCF2113AU | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controllers/drivers |
| PCF2113AU/10/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controller/driver |
| PCF2113AU/10/F4 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:LCD controllers/drivers |
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