參數(shù)資料
型號: PCD3351A
廠商: NXP Semiconductors N.V.
英文描述: 8-bit microcontrollers with DTMF generator and 128 bytes EEPROM
中文描述: 8 -雙音多頻發(fā)電機和128字節(jié)EEPROM位微控制器
文件頁數(shù): 17/36頁
文件大?。?/td> 155K
代理商: PCD3351A
1999 Oct 28
17
Philips Semiconductors
Product specification
8-bit microcontrollers with DTMF generator
and 128 bytes EEPROM
PCA3351C; 52C; 53C;
PCD3351A; 52A; 53A
From now on, it will be assumed that AD2 to AD6 will
contain the intended EEPROM page address after page
setup.
Table 18
Page setup; preset
Table 19
Page setup; auto-incrementing
7.5.2
R
EAD BYTE
SinceADDRauto-incrementsafterareadcycleregardless
of the page boundary, successive bytes can efficiently be
read by repeating the last instruction.
Table 20
Read byte
7.5.3
W
RITE PAGE
The write cycle performs a logical OR between the data in
the EEPROM latches and that in the addressed EEPROM
page. To actually copy the data from the EEPROM
INSTRUCTION
RESULT
MOVA, #addr
MOVADDR, A
MOVA, #data
MOV DATR, A
address of EEPROM latch
send address to ADDR
load write, erase/write or erase data
send data to addressed EEPROM
latch
INSTRUCTION
RESULT
MOVA, #MC2
MOV EPCR, A
MOVA, #baddr
increment mode control word
select increment mode
EEPROM Latch 0 address
(AD0 = AD1 = 0)
send EEPROM Latch 0 address to
ADDR
load 1
st
byte from Register 0
send 1
st
byte to EEPROM Latch 0
load 2
nd
byte from Register 1
send 2
nd
byte to EEPROM Latch 1
load 3
rd
byte from Register 2
send 3
rd
byte to EEPROM Latch 2
load 4
th
byte from Register 3
send 4
th
byte to EEPROM Latch 3
MOVADDR, A
MOVA, R0
MOV DATR, A
MOVA, R1
MOV DATR, A
MOVA, R2
MOV DATR, A
MOVA, R3
MOV DATR, A
INSTRUCTION
RESULT
MOVA, #RDADDR
MOVADDR, A
MOVA, DATR
load read address
send address to ADDR
read EEPROM data
latches, the corresponding bytes in the page should
previously have been erased.
The EEPROM latches are preset as described in
Section 7.5.1. The actual transfer to the EEPROM is then
performed as shown in Table 21.
The last instruction also starts Timer 2. The data in the
EEPROM latches are ORed with that in the corresponding
page bytes within 5 ms. A single-byte write is simply a
special case of ‘write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by bits AD2
to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1).
This allows efficient coding of multi-page write operations.
Table 21
Write page
7.5.4
E
RASE
/
WRITE PAGE
The EEPROM latches are preset as described in
Section 7.5.1. The page bytes corresponding to the
asserted flags (among F0 to F3) are erased and re-written
with the contents of the respective EEPROM latches.
The last instruction also starts Timer 2. Erasure takes
5 ms upon which Timer Register T2 reloads for another
5 ms cycle for writing. The top cycles together take 10 ms.
A single-byte erase/write is simply a special case of
‘erase/write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by AD2 to
AD6) and to EEPROM Latch 0 (by AD0 and AD1). This
allows efficient coding of multi-page erase/write
operations.
Table 22
Erase/write page
INSTRUCTION
RESULT
MOVA, #EWP + MC2
MOV EPCR, A
‘write page’ control word
start ‘write page’ cycle
INSTRUCTION
RESULT
MOVA, #EWP + MC3
MOV EPCR, A
‘erase/write page’ control word
start ‘erase/write page’ cycle
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