1996 Dec 18
23
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF generator,
256 bytes EEPROM and real-time clock
PCD3350A
9
DERIVATIVE INTERRUPTS
One derivative interrupt event is defined. It is controlled by
bits T2F and ET2I in the EPCR (see Tables 9 and 10).
The derivative interrupt event occurs when T2F is set. This
request is honoured under the following circumstances:
No interrupt routine proceeds
No external interrupt request is pending
The derivative interrupt is enabled
ET2I is set.
The derivative interrupt routine must include instructions
that will remove the cause of the derivative interrupt by
explicitly clearing T2F. If the derivative interrupt is not
used, T2F may directly be tested by the program.
Obviously, T2F can also be asserted under program
control, e.g. to generate a software interrupt.
Although the clock interrupt is part of a derivative function
it is linked to the external interrupt. A clock interrupt
request is honoured under the following circumstances:
No interrupt routine proceeds
No external interrupt request is pending
The enable clock interrupt bit in the derivative clock
control register is set.
10 TIMING
Although the PCD3350A operates over a clock frequency
range from 1 to 16 MHz, f
xtal
= 3.58 MHz or 10.74 MHz will
usually be chosen to take full advantage of the frequency
generator (DTMF) section.
11 RESET
In addition to the conditions given in the “PCD33xxA
Family”data sheet, all derivative registers are cleared in
the reset state.
12 IDLE MODE
In Idle mode all derivative functions remain operative, i.e.:
DTMF generator
DTMF clock divider and output
32 kHz crystal oscillator and RTC
EEPROM and Timer 2 sections.
13 STOP MODE
Since the oscillator is switched off, the frequency
generator, the EEPROM and the Timer 2 sections receive
no clock. It is suggested to clear both the HGF and the
LGF registers before entering Stop mode. This will cut off
the biasing of the internal amplifiers, considerably
reducing current requirements.
The Stop mode
must not
be entered while an erase
and/or write access to EEPROM is in progress. The STOP
instruction may only be executed when EWP in EPCR is
zero. The Timer 2 section is frozen during Stop mode.
After exit from Stop mode by a HIGH level on CE/T0,
Timer 2 proceeds from the held state.
The 32 kHz crystal oscillator and the RTC section remain
operative during Stop mode (depending only on bit RUN in
the Clock Control Register). In addition to the description
in the “PCD33xxA Family”data sheet, Stop mode may be
left by a clock interrupt event (see Chapter 9).