參數(shù)資料
型號: PCD3332-3P
廠商: NXP SEMICONDUCTORS
元件分類: 無繩電話/電話
英文描述: Multistandard pulse/tone repertory diallers/ringers
中文描述: TELEPHONE MULTIFUNCTION CKT, PDIP28
封裝: 0.600 INCH, PLASTIC, MO-015AH, SOT-117-1, DIP-28
文件頁數(shù): 7/32頁
文件大?。?/td> 154K
代理商: PCD3332-3P
1997 Jan 13
7
Philips Semiconductors
Product specification
Multistandard pulse/tone repertory
diallers/ringers
PCD3332-2; PCD3332-3;
PCD3332-S
5
FUNCTIONAL DESCRIPTION
References to the ‘PCD3332’ or the ‘device’ apply to the
PCD3332-2, the PCD3332-3 and the PCD3332-S.
5.1
Pin description
5.1.1
S
UPPLY TERMINALS
(V
DD
AND
V
SS
)
To retain data in the RAM, the standby supply voltage of
1 V, must be maintained. To ensure that the contents of
the RAM are secure in the event of a power failure, a
capacitor may be connected across the supply terminals.
The capacitor must have a suitable value to maintain the
standby voltage for a certain period of time. The minimum
operating voltage of these devices is 2.5 V. The internal
power-on reset is enabled for a voltage below this
minimum operating voltage.
5.1.2
O
SCILLATOR INPUT
/
OUTPUT
(XTAL1
AND
XTAL2)
The time base for the PCD3332 is a crystal-controlled
on-chip oscillator, which incorporates a 3.58 MHz crystal
or ceramic resonator connected between XTAL1 and
XTAL2. It should be noted that when using a ceramic
resonator, the minimum supply voltage increases.
The oscillator starts when V
DD
reaches its operating
voltage level and CE = HIGH (min. 2.5 V).
5.1.3
C
HIP ENABLE AND FREQUENCY DISCRIMINATOR
INPUT
(CE/FDI)
For DC inputs this pin acts as the chip enable (CE) input,
and is active HIGH. CE in combination with the Cradle
Switch Input (CSI) determines the mode of the device.
See Table 1.
For AC inputs the pin acts as the (ringer) Frequency
Discriminator Input (FDI).
To generate a correct ringer output tone, the input
frequency must be between 19.5 Hz and 57 Hz;
frequencies below 18 Hz and higher than 64 Hz are
omitted.
The PCD3332-3 has a second (diode selectable) range of
valid input frequencies of 14.5 Hz to 68 Hz; frequencies
below 14 Hz and higher than 76 Hz are omitted.
Ringer response timing and detection is illustrated in
Fig.15.
5.1.4
C
RADLE SWITCH INPUT
(CSI)
CSI is normally generated from the physical ‘off-hooking’
of the phone. CSI in combination with CE/FDI determines
the operating mode of the PCD3332, as shown in Table 1.
Table 1
Different modes of the PCD3332
5.1.5
R
ESET INPUT
(RESET)
RESET activates the on-chip reset circuit and is active
HIGH. The reset circuit initializes all inputs and outputs.
Two other events will cause the chip to initialize:
CE going HIGH
V
DD
falling below 2.5 V, then being restored (power-on
reset).
For this reason, RESET may not be required, and can be
connected to V
SS
. This should preferably be via a 100 k
resistor, to save leakage current.
Note that a suitable capacitor connected between V
DD
and
V
SS
will inhibit the decrease of voltage at V
DD
after a power
failure, and thus extend the time until the power-on reset is
initiated.
5.1.6
P
ULSE DIAL AND FLASH OUTPUT
(DP/FL)
This pin is the output for:
The dial pulse sequence (DP)
The calibrated LOW pulse (FL) after the FLASH key is
pressed.
The dialling sequence for pulse dialling is shown in Figs 11
and 12. DP/FL starts HIGH, pulses are LOW, and the
inter-digit pauses are HIGH. Thus, DP/FL is HIGH during
a line-make and LOW during a line-break.
If the Flash/Earth diode option is set to FLASH, then when
FLASH is pressed a LOW pulse is output, with a calibrated
duration also determined by diode option.
INPUT CSI
INPUT CE/FDI
PCD3332 STATUS
LOW
LOW
stop or power-down
mode
idle mode
ringer mode
conversation or
off-hook mode
HIGH
LOW
HIGH
LOW
HIGH
HIGH
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