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參數(shù)資料
| 型號： | PCA9675 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt |
| 中文描述： | 遠程16位I / O擴展調(diào)頻I2C總線的中斷 |
| 文件頁數(shù)： | 22/34頁 |
| 文件大小： | 185K |
| 代理商： | PCA9675 |
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PCA9675_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 1 February 2007
22 of 34
NXP Semiconductors
PCA9675
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt
13. Dynamic characteristics
[1]
t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
C
b
= total capacitance of one bus line in pF.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCLs falling edge.
[2]
[3]
[4]
[5]
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[6]
Table 6.
V
DD
= 2.3 V to 5.5 V; V
SS
= 0 V; T
amb
=
40
°
C to +85
°
C; unless otherwise specified.
Symbol
Parameter
Conditions
Dynamic characteristics
Standard mode
I
2
C-bus
Min
0
4.7
Fast mode I
2
C-bus Fast modePlus
I
2
C-bus
Min
0
0.5
Unit
Max
100
-
Min
0
1.3
Max
400
-
Max
1000
-
f
SCL
t
BUF
SCL clock frequency
bus free time between a
STOP and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid time acknowledge
time
[1]
data valid time
[2]
data set-up time
LOW period of the SCL clock
HIGH period of the SCL
clock
fall time of both SDA and
SCL signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
[6]
Port timing; C
L
≤
100 pF (see
Figure 16
and
Figure 17
)
t
v(Q)
data output valid time
t
su(D)
data input setup time
t
h(D)
data input hold time
Interrupt timing; C
L
≤
100 pF (see
Figure 16
and
Figure 17
)
t
v(D)
data input valid time
t
d(rst)
reset delay time
kHz
μ
s
t
HD;STA
4.0
-
0.6
-
0.26
-
μ
s
t
SU;STA
4.7
-
0.6
-
0.26
-
μ
s
t
SU;STO
4.0
-
0.6
-
0.26
-
μ
s
t
HD;DAT
t
VD;ACK
0
-
0
-
0
-
ns
μ
s
0.3
3.45
0.1
0.9
0.05
0.45
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
300
250
4.7
4.0
-
-
-
-
50
100
1.3
0.6
-
-
-
-
50
50
0.5
0.26
450
-
-
-
ns
ns
μ
s
μ
s
t
f
[4][5]
-
300
20 + 0.1C
b
[3]
300
-
120
ns
t
r
-
1000
20 + 0.1C
b
[3]
300
-
120
ns
t
SP
-
50
-
50
-
50
ns
-
0
4
4
-
-
-
0
4
4
-
-
-
0
4
4
-
-
μ
s
μ
s
μ
s
-
-
4
4
-
-
4
4
-
-
4
4
μ
s
μ
s
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