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  • 參數(shù)資料
    型號(hào): PCA9554D,112
    廠商: NXP Semiconductors
    文件頁(yè)數(shù): 2/35頁(yè)
    文件大?。?/td> 0K
    描述: IC I/O EXPANDER I2C 8B 16SOIC
    產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
    特色產(chǎn)品: NXP - I2C Interface
    標(biāo)準(zhǔn)包裝: 48
    接口: I²C,SM 總線
    輸入/輸出數(shù): 8
    中斷輸出:
    頻率 - 時(shí)鐘: 400kHz
    電源電壓: 2.3 V ~ 5.5 V
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
    供應(yīng)商設(shè)備封裝: 16-SO
    包裝: 管件
    包括: POR
    產(chǎn)品目錄頁(yè)面: 826 (CN2011-ZH PDF)
    配用: 568-4002-ND - DEMO BOARD I2C
    其它名稱: 568-1053-5
    935269192112
    PCA9554D
    PCA9554_9554A
    All information provided in this document is subject to legal disclaimers.
    NXP B.V. 2013. All rights reserved.
    Product data sheet
    Rev. 9 — 19 March 2013
    10 of 35
    NXP Semiconductors
    PCA9554; PCA9554A
    8-bit I2C-bus and SMBus I/O port with interrupt
    6.5 Device address
    6.6 Bus transactions
    Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown
    in Figure 11 and Figure 12. Data is read from the PCA9554/PCA9554A registers using the
    Read mode as shown in Figure 13 and Figure 14. These devices do not implement an
    auto-increment function, so once a command byte has been sent, the register which was
    addressed will continue to be accessed by reads until a new command byte has been
    sent.
    Fig 9.
    PCA9554 device address
    Fig 10. PCA9554A device address
    002aac494
    0
    1
    0
    A2
    A1
    A0 R/W
    fixed
    slave address
    hardware
    selectable
    002aac495
    0
    1
    A2
    A1
    A0 R/W
    fixed
    slave address
    hardware
    selectable
    Fig 11. Write to Output Port register
    1
    0
    A2 A1 A0
    0
    A
    S0
    START condition
    R/W
    acknowledge
    from slave
    002aac472
    A
    acknowledge
    from slave
    SCL
    SDA
    A
    write to port
    data out
    from port
    P
    tv(Q)
    9
    8
    7
    6
    5
    4
    3
    2
    1
    command byte
    acknowledge
    from slave
    data to port
    DATA 1
    slave address
    0000001
    0
    STOP
    condition
    data 1 valid
    Fig 12. Write to Configuration register or Polarity Inversion register
    1
    0
    A2 A1 A0
    0
    A
    S0
    START condition
    R/W
    acknowledge
    from slave
    002aac473
    A
    acknowledge
    from slave
    SCL
    SDA
    A
    data to
    register
    P
    9
    8
    7
    6
    5
    4
    3
    2
    1
    command byte
    acknowledge
    from slave
    data to register
    DATA
    slave address
    000001 1/0
    0
    STOP
    condition
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