參數(shù)資料
型號(hào)： PCA9535PW,118
廠商： NXP Semiconductors
文件頁數(shù)： 25/26頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 16B 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
接口： I²C，SM 總線
輸入/輸出數(shù)： 16
中斷輸出： 是
頻率 - 時(shí)鐘： 400kHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
包括： POR
其它名稱： 935273946118
PCA9535PW-T
PCA9535PW-T-ND
PCA9535_PCA9535C_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 15 September 2008
8 of 31
NXP Semiconductors
PCA9535; PCA9535C
16-bit I2C-bus and SMBus, low power I/O port with interrupt
6.2.5 Registers 6 and 7: Conguration registers
This register congures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. At reset, the device's ports are inputs.
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9535/PCA9535C
in a reset condition until VDD has reached VPOR. At that point, the reset condition is
released and the PCA9535/PCA9535C registers and SMBus state machine will initialize
to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 I/O port
When an I/O is congured as an input on PCA9535, FETs Q1 and Q2 are off, creating a
high impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
In the case of PCA9535C, FET Q1 has been removed and the open-drain FET Q2 will
function the same as PCA9535.
If the I/O is congured as an output, then on PCA9535 either Q1 or Q2 is on, depending
on the state of the Output Port register. Care should be exercised if an external voltage is
applied to an I/O congured as an output because of the low-impedance path that exists
between the pin and either VDD or VSS.
Table 11.
Conguration port 0 register
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
11111111
Table 12.
Conguration port 1 register
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
11111111
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