參數(shù)資料
型號(hào)： PCA5007
廠商： NXP Semiconductors N.V.
英文描述： Pager baseband controller
中文描述： 傳呼機(jī)基帶控制器
文件頁(yè)數(shù)： 20/112頁(yè)
文件大?。?/td> 604K
代理商： PCA5007
1998 Oct 07
20
Philips Semiconductors
Product specification
Pager baseband controller
PCA5007
6.8
I
2
C-bus serial I/O
The serial port supports the 2-line I
2
C-bus which consists
of a data line (SDA) and a clock line (SCL). These lines
also function as the I/O port lines P1.7 and P1.6
respectively. The system is unique because data
transport, clock generation, address recognition and bus
control arbitration are all controlled by hardware.
The I
2
C-bus serial I/O has complete autonomy in byte
handling. The implementation in the PCA5007 operates in
single master mode as:
Master transmitter
Master receiver.
These functions are controlled by the S1CON register.
S1STA is the status register whose contents may also be
used as a vector to various service routines. S1DAT is the
data shift register. The block diagram of the I
2
C-bus
serial I/O is shown in Fig.8.
6.8.1
D
IFFERENCES TO A STANDARD
I
2
C-
BUS INTERFACE
The I
2
C-bus interface of the PCA5007 implements the
standard for master receiver and transmitter as defined in
e.g. P83CL781/782 with the following restrictions:
The baud rate is fixed to 100 kHz derived from the
on-chip 6 MHz oscillator. Therefore bits CR0, CR1 and
CR2 in the S1CON SFR are not available.
Only single master functions are implemented.
– Slave address (S1ADR) is not available
– Status register (S1STA) reports only status defined
for the MST/TRX and MST/REC modes
– Multimaster operation is not supported.
Fig.8 Block diagram of I
2
C-bus serial I/O.
handbook, full pagewidth
MGL449
SHIFT REGISTER
S1DAT
SDA
ARBITRATION LOGIC
SCL
BUS CLOCK GENERATOR
S1STA
I
7
6
5
4
3
2
1
0
S1CON
7
6
5
4
3
2
1
0
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