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參數(shù)資料
| 型號： | PCA1604 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 32 kHz watch circuits with EEPROM |
| 中文描述： | 32千赫的EEPROM的手表電路 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 85K |
| 代理商： | PCA1604 |
1997 Dec 12
3
Philips Semiconductors
Product specification
32 kHz watch circuits with EEPROM
PCA16xx series
PINNING
SYMBOL
PIN
DESCRIPTION
V
SS
TEST
OSC IN
OSC OUT
V
DD
M1
M2
RESET
1
2
3
4
5
6
7
8
ground (0 V)
test output
oscillator input
oscillator output
positive supply voltage
motor 1 output
motor 2 output
reset input
Fig.1 Pin configuration, PCA16xxT, (PMFP8).
1
2
3
4
8
7
6
5
PCA16xxT
VSS
TEST
OSC IN
OSC OUT
RESET
M2
M1
VDD
MSA973
FUNCTIONAL DESCRIPTION AND TESTING
Motor pulse
The motor pulse width (t
P
) and the cycle times (t
T
) are
given in Chapter “Available types”.
Voltage level detector
The supply voltage is compared with the internal voltage
reference V
LIT
and V
EOL
every minute. The first voltage
level detection is carried out 30 ms after a RESET.
Lithium mode
If a lithium voltage is detected (V
DD
≥
V
LIT
), the circuit will
operate in the lithium mode. The motor pulse will be
produced with a 75% duty factor.
Silver-oxide mode
If the voltage level detected is between V
LIT
and V
EOL
, the
circuit will operate in silver-oxide mode.
Battery end-of-life
(1)
If the battery end-of-life is detected (V
DD
≤
V
EOL
), the
motor pulse will be produced without chopping. To indicate
this condition, bursts of 4 pulses are produced every 4 s.
Power-on reset
For correct operation of the Power-on reset the rise time of
V
DD
from 0 V to 2.1 V should be less than 0.1 ms.
All resettable flip-flops are reset. Additionally the polarity of
the first motor pulse is positive: V
M1
V
M2
≥
0 V.
(1) Only available for types with a 1 s motor pulse.
Customer testing
An output frequency of 32 Hz is provided at RESET (pin 8)
to be used for exact frequency measurement. Every
minute a jitter occurs as a result of time calibration, which
occurs 90 to 150 ms after disconnecting the RESET from
V
DD
.
Connecting the RESET to V
DD
stops the motor pulses
leaving them in a HIGH impedance 3-state condition and a
32 Hz signal without jitter is produced at the TEST pin.
A debounce circuit protects accidental stoppages due to
mechanical shock to the watch (t
DEB
= 14.7 to 123.2 ms).
Connecting RESET to V
SS
activates Tests 1 and 2 and
disables the time calibration.
Test 1, V
DD
> V
EOL
. Normal function takes place except
the voltage detection cycle (t
V
) is 125 ms and the cycle
time t
T1
is 31.25 ms. At pin TEST a minute signal is
available at 8192 times its normal frequency.
Test 2
(2)
, V
DD
< V
EOL
. The voltage detection cycle (t
V
) is
31.25 ms and the motor pulse period (t
T2
) = 31.25 ms.
Test and reset mode are terminated by disconnecting the
RESET pin.
Test 3, V
DD
> 5.1 V
. Motor pulses with a time period of
t
T3
= 31.25 ms and n
×
122
μ
s are produced to check the
contents of the EEPROM. At pin TEST the motor pulse
period signal (t
T
) is available at 1024 times its normal
frequency. The circuit returns to normal operation when
V
DD
< 2.5 V between two motor pulses.
(2) Only applicable for types with the battery end-of-life detector.
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