參數(shù)資料
型號: PC9S08QE128CLH
廠商: Freescale Semiconductor
文件頁數(shù): 18/50頁
文件大?。?/td> 0K
描述: MCU 8BIT 128K FLASH 64-LQFP
標準包裝: 160
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 50MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 22x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
Electrical Characteristics
MC9S08QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
25
Figure 17. Reset Timing
Figure 18. IRQ/KBIPx Timing
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
8
31
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
7
24
ns
10
Voltage regulator recovery time
tVRR
—4
μs
1 Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated.
2 This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 85°C.
Table 13. Control Timing (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
textrst
RESET PIN
tIHIL
KBIPx
tILIH
IRQ/KBIPx
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