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參數(shù)資料
| 型號(hào)： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
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13
PC7410M16
2183A–HIREL–12/02
Power Consideration
Power Management
The PC7410M16 provides four power modes, selectable by setting the appropriate con-
trol bits in the MSR and HIDO registers. The four power modes are:
Full-power: This is the default power state of the PC7410M16. The PC7410M16 is
fully powered and the internal functional units are operating at the full processor
clock speed. If the dynamic power management mode is enabled, functional units
that are idle will automatically enter a low-power state without affecting
performance, software execution or external hardware.
Doze: All the functional units of the PC7410M16 are disabled except for the time
base/decrementer registers and the bus snooping logic. When the processor is in
doze mode, an external asynchronous interrupt, a system management interrupt, a
decrementer exception, a hard or soft reset or machine check brings the
PC7410M16 into the full-power state. The PC7410M16 in doze mode maintains the
PLL in a fully powered state and locked to the system external clock input (SYSCLK)
so a transition to the full-power state takes only a few processor clock cycles.
Nap: The nap mode further reduces power consumption by disabling bus snooping,
leaving only the time base register and the PLL in a powered state. The
PC7410M16 returns to the full-power state upon receipt of an external
asynchronous interrupt, a system management interrupt, a decrementer exception,
a hard or soft reset or a machine check input (MCP). A return to full-power state
from a nap state takes only a few processor clock cycles. When the processor is in
nap mode, if QACK is negated, the processor is put in doze mode to support
snooping.
Sleep: Sleep mode minimizes power consumption by disabling all internal functional
units, after which external system logic may disable the PLL and SYSCLK.
Returning the PC7410M16 to the full-power state requires the enabling of the PLL
and SYSCLK, followed by the assertion of an external asynchronous interrupt, a
system management interrupt, a hard or soft reset or a machine check input (MCP)
signal after the time required to relock the PLL.
21
L2IO
L2 Instruction-Only. Setting this bit enables instruction-only operation in the L2 cache. For this operation, only
transactions from the L1 instruction cache are allowed to be reloaded in the L2 cache. Data addresses
already in the cache will still hit for the L1 data cache. When both L2DO and L2IO are asserted, the L2 cache
is effectively locked.
22
L2CLKSTP
L2 Clock Stop. Setting this bit enables the automatic stopping of the L2CLK_OUT signals for cache rams that
support this function. While L2CLKSTP is set, the L2CLK_OUT signals will automatically be stopped when
PC7410M16 enters nap or sleep mode, and automatically restarted when PC7410M16 exits nap or sleep.
23
L2DRO
L2 DLL rollover. Setting this bit enables a potential rollover (or actual rollover) condition of the DLL to cause a
checkstop for the processor. A potential rollover condition occurs when the DLL is selecting the last tap of the
delay line, and thus may risk rolling over to the first tap with one adjustment while in the process of keeping
synchronized. Such a condition is improper operation for the DLL, and, while this condition is not expected, it
allows detection for added security. This bit can be set when the DLL is first enabled (set with the L2CLK bits)
to detect rollover during initial synchronization. It could also be set when the L2 cache is enabled (with L2E
bit) after the DLL has achieved its initial lock.
24-30
–
Reserved
31
L2IP
L2 global invalidate in progress (read only) – See the Motorola user's manual for L2 Invalidation procedure.
Table 4.
L2CR Bit Settings (Continued)
Bit
Name
Function
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