參數(shù)資料
型號： PALCE16V8
廠商： Lattice Semiconductor Corporation
英文描述： EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic
中文描述： 電子工程的CMOS零功率20引腳通用可編程陣列邏輯
文件頁數(shù)： 27/32頁
文件大?。?/td> 634K
代理商： PALCE16V8
4
PALCE16V8 and PALCE16V8Z Families
USE
GAL
DEVICES
FOR
NEW
DESIGNS
Registered Output Conguration
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered
conguration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1x. The ip-op is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Congurations
The PALCE16V8 has three combinatorial output congurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Conguration
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except
for MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals
are pins 1 and 11. These congurations are summarized in Table 1 and illustrated in Figure 2.
Table 1. Macrocell Conguration
SG0
SG1
SL0X
Cell
Conguration
Devices
Emulated
SG0
SG1
SL0X
Cell
Conguration
Devices
Emulated
Device Uses Registers
Device Uses No Registers
0
1
0
Registered Output
PAL16R8, 16R6,
16R4
100
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
011
Combinatorial
I/O
PAL16R6, 16R4
1
0
1
Input
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
111
Combinatorial
I/O
PAL16L8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PALCE16V8 AND PALCE16V8Z FAMILIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EE CMOS (Zero-Power) 20-Pin Universal Programmable Array Logic
PALCE16V8-10 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8100DMB 制造商:CYPRESS 功能描述:*
PALCE16V8-10DMB 制造商:Cypress Semiconductor 功能描述:
PALCE16V8-10JC 制造商:Cypress Semiconductor 功能描述:
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