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參數(shù)資料
| 型號(hào)： | PAC7142 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Microcontroller Family Hardware Specifications |
| 中文描述： | 微控制器系列硬件規(guī)格 |
| 文件頁數(shù)： | 17/56頁 |
| 文件大?。?/td> | 471K |
| 代理商： | PAC7142 |
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Electrical Characteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
17
The capacitance C
P
should be chosen in the range of:
Eqn. 14
The stabilization delays shown in
Table 20
are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1
With each transition of the clock
f
CMP
, the deviation from the reference clock
f
REF
is measured and input
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in
Figure 4
. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
Jitter Information
Figure 4. Jitter Definitions
The relative deviation of t
NOM
is at its maximum for one clock period, and decreases towards zero for
larger number of clock periods (N). Thus, jitter is defined as:
Eqn. 15
For N
<
100, the following equation is a good fit for the maximum jitter:
Eqn. 16
Figure 5. Maximum Bus Clock Jitter Approximation
C
S
20
÷
C
P
C
S
10
÷
≤
≤
0
t
MIN1
t
NOM
t
MAX1
1
2
3
N–1
N
t
MIN
(N)
t
MAX
(N)
J N
max
1
t
N
N t
NOM
-------------------
–
1
t
N
N t
NOM
-------------------
–
,
=
J N
j
1
N
-------
j
2
+
=
0 1
5
10
20
15
N
J(N)
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