參數(shù)資料
型號(hào)： PAC7101
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 19/56頁(yè)
文件大小： 471K
代理商： PAC7101
Electrical Characteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
19
3.8.6
Startup
Table 23
summarizes several startup characteristics.
Refer to Section 4.3.6.10, “CRG Operating Mode
Details,” in the
MAC7100 Microcontroller Family Reference Manual
(MAC7100RM) for details.
3.8.6.1
The V
PORR
and V
PORA
levels are derived from V
DD
2.5. The V
LVRA
level is derived from V
DD
2.5. They
are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and
clock quality checks start. After t
CQOUT
(
Table 19
,
J4
) if no valid oscillation is detected, the MCU will
start using the internal self-generated clock. The minimum startup time is given by t
uposc
(
Table 19
,
J3
).
Power On and Low Voltage Reset (POR and LVR)
3.8.6.2
SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.
SRAM Data Retention
3.8.6.3
When external reset is asserted for a time greater than PW
RSTL
, the CRG generates an internal reset and
the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.
External Reset
3.8.6.4
The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays
occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and
return to full performance mode (this assumes that the internal regulator is used rather than driving V
DD
2.5
and V
DD
PLL with an external regulator). Second, a clock quality check is performed in the same manner
as for a power-on reset before releasing the clocks to the system.
Stop Recovery
3.8.6.5
Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since
the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by
internal or external interrupts.
Pseudo Stop Recovery
3.8.6.6
Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned
to run mode by internal or external interrupts.
Doze Recovery
Table 23. CRG Startup Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
L1
D Reset input pulse width
PW
RSTL
2
—
—
t
OSC
L2
D Startup from Reset
n
RST
192
—
196
t
OSC
L3
D XIRQ, IRQ pulse width, edge-sensitive mode
PW
IRQ
20
—
—
ns
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