參數(shù)資料
型號(hào)： PA28F400BL-B150
廠商： INTEL CORP
元件分類： PROM
英文描述： 4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
中文描述： 512K X 8 FLASH 12V PROM, 150 ns, PDSO44
封裝： 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁數(shù)： 29/50頁
文件大?。?/td> 559K
代理商： PA28F400BL-B150
28F400BX-T/B, 28F004BX-T/B
4.5.4 RESET/DEEP POWERDOWN
The 4-Mbit boot block flash family supports a typical
I
CC
of 0.2
m
A in deep power-down mode. One of the
target markets for these devices is in portable equip-
ment where the power consumption of the machine
is of prime importance. The 4-Mbit boot block flash
family has a RP
Y
pin which places the device in the
deep powerdown mode. When RP
Y
is at a logic-low
(GND
g
0.2V), all circuits are turned off and the de-
vice typically draws 0.2
m
A of V
CC
current.
During read modes, the RP
Y
pin going low dese-
lects the memory and places the output drivers in a
high impedance state. Recovery from the deep pow-
er-down state, requires a maximum of 300 ns to ac-
cess valid data (t
PHQV
).
During erase or program modes, RP
Y
low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP
Y
function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2
m
A current level.
RP
Y
transitions to V
IL
or turning power off to the
device will clear the status register.
This use of RP
Y
during system reset is important
with automated write/erase devices. When the sys-
tem comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel’s
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
Y
input. In this application RP
Y
is controlled by the
same RESET
Y
signal that resets the system CPU.
4.6 Power-up Operation
The 4-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon power-
up the 4-Mbit boot block flash family is indifferent as
to which power supply, V
PP
or V
CC
, powers-up first.
Power supply sequencing is not required.
The 4-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CE
Y
low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for V
CC
voltages above V
LKO
when V
PP
is
active. Since both WE
Y
and CE
Y
must be low for a
command write, driving either signal to V
IH
will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of mem-
ory contents can only occur after successful com-
pletion of the two-step command sequences. Finally
the device is disabled until RP
Y
is brought to V
IH
,
regardless of the state of its control inputs. This fea-
ture provides yet another level of memory protec-
tion.
4.7 Power Supply Decoupling
Flash memory’s power switching characteristics re-
quire careful device decoupling methods. System
designers are interested in 3 supply current issues:
#
Standby current levels (I
CCS
)
#
Active current levels (I
CCR
)
#
Transient peaks produced by falling and rising
edges of CE
Y
.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1
m
F ceramic capacitor
connected between each V
CC
and GND, and be-
tween its V
PP
and GND. These high frequency, low-
inherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 V
PP
TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
V
PP
power supply trace by the printed circuit board
designer. The V
PP
pin supplies the flash memory
cells current for programming and erasing. One
should use similar trace widths and layout consider-
ations given to the V
CC
power supply trace. Ade-
quate V
PP
supply traces and decoupling will de-
crease spikes and overshoots.
4.7.2 V
CC
, V
PP
AND RP
Y
TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by V
PP
or CE
Y
tran-
sitions or WSM actions. Its state upon power-up, af-
ter exit from deep power-down mode or after V
CC
transitions below V
LKO
(Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after V
PP
transitions down to
V
PPL
, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.
29
相關(guān)PDF資料
PDF描述
PA28F400BV-B80 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BV-T80 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVB120 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVT60 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVT80 4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PA28F400BL-T150 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBlT (256K x 16, 512K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVB120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVB60 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BV-B60 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
PA28F400BVB80 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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