參數(shù)資料
型號(hào): PA28F400B5B80
廠商: INTEL CORP
元件分類(lèi): PROM
英文描述: SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
中文描述: 512K X 8 FLASH 5V PROM, 80 ns, PDSO44
封裝: 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁(yè)數(shù): 20/38頁(yè)
文件大?。?/td> 501K
代理商: PA28F400B5B80
SMART 5 BOOT BLOCK MEMORY FAMILY
E
20
ADVANCE INFORMATION
Table 7. Status Register Bit Definition
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
(WSMS)
Check WSM bit first to determine word/byte
program or block erase completion, before
checking program or erase status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” one of the following has
occurred:
1. V
PP
out of range.
2. WSM has applied the max number of erase
pulses to the block and is still unable to verify
successful block erasure.
3. Erase Set-Up command was followed by a
command other than Erase Confirm.
When this bit is set to “1,” one of the following has
occurred:
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
1. V
PP
out of range.
2. WSM has applied the max number of program
pulses and is still unable to verify a successful
program.
3. Erase Set-Up command was followed by a
command other than Erase Confirm.
The V
PP
status bit does not provide continuous
indication of V
PP
level. The WSM interrogates V
PP
level only after the Program or Erase command
sequences have been entered, and informs the
system if V
PP
is out of range. The V
PP
status bit is
not guaranteed to report accurate feedback
between V
PPLK
and V
PPH
.
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.2–SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and should
be masked out when polling the status register.
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