參數(shù)資料
型號: PA28F200BX-B80
廠商: INTEL CORP
元件分類: PROM
英文描述: 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述: 128K X 16 FLASH 12V PROM, 80 ns, PDSO44
封裝: 1.110 X 0.525 INCH, PLASTIC, SOP-44
文件頁數(shù): 34/48頁
文件大?。?/td> 562K
代理商: PA28F200BX-B80
28F200BX-T/B, 28F002BX-T/B
AC CHARACTERISTICSDRead Only Operations
(1)
Versions
V
CC
g
5%
28F200BX-60
(4)
28F200BX-60
(5)
28F200BX-80
(5)
28F200BX-120
(5)
28F002BX-60
(4)
28F002BX-60
(5)
28F002BX-80
(5)
28F002BX-120
(5)
V
CC
g
10%
Unit
Symbol
Parameter
Notes
Min
Max
Min
Max
Min
Max
Min
Max
t
AVAV
t
RC
Read Cycle Time
60
70
80
120
ns
t
AVQV
t
ACC
Address to
60
70
80
120
ns
Output Delay
t
ELQV
t
CE
t
PHQV
t
PWH
RP
Y
High to
Output Delay
CE
Y
to Output Delay
2
60
70
80
120
ns
300
300
300
300
ns
t
GLQV
t
OE
OE
Y
to Output Delay
2
30
35
40
40
ns
t
ELQX
t
LZ
CE
Y
to Output Low Z
3
0
0
0
0
ns
t
EHQZ
t
HZ
CE
Y
High to Output
High Z
3
20
25
30
30
ns
t
GLQX
t
OLZ
OE
Y
to Output Low Z
OE
Y
High to Output
High Z
3
0
0
0
0
ns
t
GHQZ
t
DF
3
20
25
30
30
ns
t
OH
Output Hold from
Addresses,
CE
Y
or OE
Y
Change,
Whichever is First
3
0
0
0
0
ns
t
IR
Input Rise Time
10
10
10
10
ns
t
IF
Input Fall Time
10
10
10
10
ns
t
ELFL
t
ELFH
CE
Y
to BYTE
Y
Switching
Low or High
3
5
5
5
5
ns
t
FHQV
BYTE
Y
Switching
High to
Valid Output Delay
3, 6
60
70
80
120
ns
t
FLQZ
BYTE
Y
Switching
Low to
Output High Z
3
20
25
30
30
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE
Y
may be delayed up to t
CE
–t
OE
after the falling edge of CE
Y
without impact on t
CE
.
3. Sampled, not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
6. t
FLQV
, BYTE
Y
switching low to valid output delay, will be equal to t
AVQV
, measured from the time DQ
15
/A-
1
becomes
valid.
34
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