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參數(shù)資料
| 型號： | PA28F200BV-T80 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | POWERLINE: RP40-S_D_TE - 2:1 Wide Input Voltage Range- 40 Watts Output Power- 1.6kVDC Isolation- Fixed Operating Frequency- Six-Sided Continuous Shield- Design Meet Safety Standard- Standard 76.2 x66.0x10.2mm Package- Efficiency to 90% |
| 中文描述： | 256K X 8 FLASH 5V PROM, 150 ns, PDSO44 |
| 封裝： | 0.525 X 1.110 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 562K |
| 代理商： | PA28F200BV-T80 |
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28F200BX-T/B, 28F002BX-T/B
Table 4. Command Definitions
Command
Bus
Cycles
Req’d
Notes
First Bus Cycle
Second Bus Cycle
8
Operation Address Data Operation Address Data
Read Array/Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2, 4
Write
X
90H
Read
IA
IID
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
BA
D0H
Word/Byte Write Setup/Write
2
6, 7
Write
WA
40H
Write
WA
WD
Erase Suspend/Erase Resume
2
Write
X
B0H
Write
X
D0H
Alternate Word/Byte Write Setup/Write
2
6, 7
Write
WA
10H
Write
WA
WD
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA
e
Identifier Address: 00H for manufacturer code, 01H for device code.
3. SRD
e
Data read from Status Register.
4. IID
e
Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA
e
Address within the block being erased.
6. WA
e
Address to be written.
WD
e
Data to be written at location PA.
7. Either 40H or 10H command is valid.
8. When writing commands to the device, the upper data bus
[
DQ8–DQ15
]
e
X (28F200BX-only) which is either V
CC
or
V
SS
to avoid burning additional current.
Invalid/Reserved
These are unassigned commands. It is not recom-
mended that the customer use any command other
than the valid commands specified above. Intel re-
serves the right to redefine these codes for future
functions.
Read Array (FFH)
This single write command points the read path at
the array. If the host CPU performs a CE
Y
/OE
Y
controlled read immediately following a two-write se-
quence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Inteligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address A0 is used in this mode, all
other address inputs are ignored).
Read Status Register (70H)
This is one of the two commands that is executable
while the state machine is operating. After this com-
mand is written, a read of the device will output the
contents of the status register, regardless of the ad-
dress presented to the device.
The device automatically enters this mode after pro-
gram or erase has completed.
Clear Status Register (50H)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchro-
nization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after pro-
gramming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.
19
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