參數(shù)資料
型號(hào): PA28F200B5T80
廠商: INTEL CORP
元件分類: PROM
英文描述: SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT
中文描述: 256K X 8 FLASH 5V PROM, 80 ns, PDSO44
封裝: 0.525 X 1.110 INCH, PLASTIC, SOP-44
文件頁(yè)數(shù): 31/38頁(yè)
文件大?。?/td> 501K
代理商: PA28F200B5T80
E
5.5
SMART 5 BOOT BLOCK MEMORY FAMILY
31
ADVANCE INFORMATION
AC Characteristics
—Read Operations—Commercial and Extended
Temperature
Temp
Commercial
Extended
Speed
-60/-70
-80/-90
-80/-90
#
Sym
Parameter
V
CC
5V
±
5%
(4)
5V
±
10%
(5)
5V
±
10%
(5)
5V
±
10%
(5)
Unit
Load
30 pF
100 pF
100 pF
100 pF
Notes
Min
Max
Min
Max
Min
Max
Min
Max
R1
t
AVAV
Read Cycle
2, 4 Mbit
60
70
80
80
ns
Time
8 Mbit
70
80
90
90
ns
R2
t
AVQV
Address to
2, 4 Mbit
60
70
80
80
ns
Output Delay
8 Mbit
70
80
90
90
ns
R3
t
ELQV
CE# to
2, 4 Mbit
2
60
70
80
80
ns
Output Delay
8 Mbit
70
80
90
90
ns
R4
t
GLQV
OE# to Output Delay
2
30
35
40
40
ns
R5
t
PHQV
RP# to Output Delay
450
450
450
450
ns
R6
t
ELQX
CE# to Output in Low Z
3
0
0
0
0
ns
R7
t
GLQX
OE# to Output in Low Z
3
0
0
0
0
ns
R8
t
EHQZ
CE# to Output in High Z
3
20
20
20
25
ns
R9
t
GHQZ
OE# to Output in High Z
3
20
20
20
25
ns
R10
t
OH
Output Hold from Address,
CE#, or OE# Change,
Whichever Occurs First
3
0
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to t
CE
–t
OE
after the falling edge of CE# without impact on t
CE
.
3. Sampled, but not 100% tested.
4. See
Test Configuration
(Figure 13), 5 V High-Speed Test component values.
5. See
Test Configuration
(Figure 13), 5 V Standard Test component values.
6. Dynamic BYTE# switching between word and byte modes is not supported. Mode changes must be made when the device
is in deep power-down or powered down.
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