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參數(shù)資料
| 型號(hào)： | P8XC591 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | HiRel FPGA, Low-Power 1.0?? CMOS Technology |
| 中文描述： | 單芯片8 - CAN控制器位微控制器 |
| 文件頁(yè)數(shù)： | 124/160頁(yè) |
| 文件大小： | 601K |
| 代理商： | P8XC591 |
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2000 Jul 26
124
Philips Semiconductors
Preliminary Specification
Single-chip 8-bit microcontroller with CAN controller
P8xC591
19 PORT 1 OPERATION
Port 1 may be used to input up to 6 analog signals ADC.
Unused ADC inputs may be used to input digital inputs.
These inputs have an inherent hysteresis to prevent the
input logic from drawing excessive current from the power
lines when driven by analog signals. Channel to channel
crosstalk (Ct) should be taken into consideration when
both analog and digital signals are simultaneously input to
Port 3 (see Chapter 24 “DC Characteristics”).
20 ANALOG-TO-DIGITAL CONVERTER (ADC)
20.1
ADC features
10-bit resolution
6 multiplexed analog inputs
Start of a conversion by software or with an external
signal
Conversion time for one 10-bit analog-to-digital
conversion: 25
μ
s @ 12 MHz
Differential non-linearity (DL
e
): ±
1 LSB
Integral non-linearity (IL
e
):
±
2 LSB
Offset error (OS
e
): ±
2 LSB
Gain error (G
e
):
±
4%
Absolute voltage error (A
e
): 3 LSB
Channel-to-channel matching (M
ctc
):
±
1 LSB
Crosstalk between analog inputs (C
t
): < 60 dB at
100 kHz
Monotonic and no missing codes
Separated analog (V
SSA
) and digital (V
DD
, V
SS
) supply
voltages
Reference voltage special pin: V
ref(p)(A)
.
For information on the ADC characteristics, refer to
Chapter 24.
20.2
ADC functional description
The analog input circuitry consists of an 6-input analog
multiplexer and a 10-bit, straight binary, successive
approximation ADC. The A/D can also be operated in 8-bit
mode with faster conversion times by setting bit ADC8
(AUXR1.7). The 8-bit result will be contained in the ADCH
register. The analog reference voltage and analog power
supplies are connected via separate input pins. For 10-bit
accuracy, the conversion takes 50 machine cycles, i.e.,
25
μ
s at an oscillator frequency of 12 MHz. For the 8-bit
mode, the conversion takes 24 machine cycles. Input
voltage swing is from 0 V to +5 V. Because the internal
DAC employs a ratiometric potentiometer, there are no
discontinouties in the converter characteristic. Figure 48
shows a functional diagram of the analog input circuitry.
The ADC has the option of either being powered off in Idle
mode for reduced power consumption or being active in
the Idle mode for reducing internal noise during the
conversion. This option is selected by the AIDL bit of
AUXR1register(AUXR1.6).WiththeAIDLbitset,theADC
is active in the Idle mode, and with the AIDL bit cleared,
the ADC is powered off in Idle mode.
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