參數(shù)資料
型號(hào): P89LPC954FBD44,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 3/69頁(yè)
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
標(biāo)準(zhǔn)包裝: 160
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
11 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P1.5/RST
47
5
43
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or maybe a
reset input/output if selected via UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above
12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until VDD has reached its
specied level. When system power is removed VDD will
fall below the minimum specied operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when VDD
falls below the minimum specied operating voltage.
P1.6
46
4
42
I/O
P1.6 — Port 1 bit 6.
P1.7/AD04
43
2
40
I/O
P1.7 — Port 1 bit 7.
I
AD04 — ADC0 channel 4 analog input.
P2.0 to P2.5
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-congurable
output type. During reset Port 2 latches are congured in the
input only mode with the internal pull-up disabled. The
operation of Port 2 pins as inputs and outputs depends upon
the port conguration selected. Each port pin is congured
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
P2.0/AD07
42
1
39
I/O
P2.0 — Port 2 bit 0.
I
AD07 — ADC0 channel 7 analog input.
P2.1/AD06
41
44
38
I/O
P2.1 — Port 2 bit 1.
I
AD06 — ADC0 channel 6 analog input.
P2.2/MOSI
30
34
28
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When congured as
master, this pin is output; when congured as slave, this pin
is input.
P2.3/MISO
29
33
27
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When congured as master, this pin is input, when
congured as slave, this pin is output.
P2.4/SS
28
32
26
I/O
P2.4 — Port 2 bit 4.
I/O
SS — SPI Slave select.
Table 3.
Pin description …continued
Symbol
Pin
Type Description
LQFP48
PLCC44
LQFP44
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