參數(shù)資料
型號: P89LPC9331FDH,512
廠商: NXP Semiconductors
文件頁數(shù): 76/94頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 4K 28-TSSOP
標(biāo)準(zhǔn)包裝: 51
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b; D/A 2x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
配用: 568-1758-ND - BOARD EVAL FOR LPC93X MCU FAMILY
其它名稱: 935288633512
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5.1 — 20 August 2012
78 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 15.
Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V unless otherwise specified.
Tamb = 40 Cto+85 C for industrial applications, 40 Cto+125 C extended, unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =18MHz
Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to
1% at
Tamb =25 C; clock
doubler option = OFF
(default)
7.189
7.557
7.189
7.557
MHz
nominal f = 14.7456 MHz;
clock doubler option = ON
14.378
15.114
14.378 15.114 MHz
fosc(WD)
internal watchdog
oscillator frequency
Tamb =25 C
380
420
380
420
kHz
fosc
oscillator frequency
0
18
-
MHz
Tcy(clk)
clock cycle time
55
-
ns
fCLKLP
low-power select clock
frequency
08
-
MHz
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
-
50
ns
any pin except P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
22
Tcy(clk) tCLCX
22
-
ns
tCLCX
clock LOW time
22
Tcy(clk) tCHCX
22
-
ns
tCLCH
clock rise time
-5
-
5
ns
tCHCL
clock fall time
-5
-
5
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle
time
16Tcy(clk)
-
888
-
ns
tQVXH
output data set-up to
clock rising edge time
13Tcy(clk)
-
722
-
ns
tXHQX
output data hold after
clock rising edge time
-Tcy(clk) + 20
-
75
ns
tXHDX
input data hold after
clock rising edge time
-0
-
0
ns
tXHDV
input data valid to clock
rising edge time
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK6
03.0
MHz
master
-
CCLK4
-4.5
MHz
TSPICYC
SPI cycle time
slave
6CCLK
-
333
-
ns
master
4CCLK
-
222
-
ns
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