參數(shù)資料
型號(hào)： P89LPC921
廠商： NXP Semiconductors N.V.
英文描述： MINIATURE POWER RELAY
中文描述： 8位微控制器兩個(gè)小時(shí)80C51的核心2鍵盤(pán)/ 4 KB的/ 8 KB的3伏的低功耗Flash 256 - RAM的字節(jié)數(shù)據(jù)
文件頁(yè)數(shù)： 17/45頁(yè)
文件大?。?/td> 877K
代理商： P89LPC921
Philips Semiconductors
P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 06 — 21 November 2003
17 of 45
9397 750 12285
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8.10 Data RAM arrangement
The 256 bytes of on-chip RAM are organized as shown in
Table 5
.
8.11 Interrupts
The P89LPC920/921/922 uses a four priority level interrupt structure. This allows
great flexibility in controlling the handling of the many interrupt sources. The
P89LPC920/921/922 supports 12 interrupt sources: external interrupts 0 and 1,
timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout
detect, watchdog/real-time clock, I
2
C, keyboard, and comparators 1 and 2.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
8.11.1
External interrupt inputs
The P89LPC920/921/922 has two external interrupt inputs as well as the Keypad
Interrupt function. The two interrupt inputs are identical to those present on the
standard 80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
If an external interrupt is enabled when the P89LPC920/921/922 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and
resume operation. Refer to
Section 8.14 “Power reduction modes”
for details.
Table 5:
Type
DATA
IDATA
On-chip data memory usages
Data RAM
Memory that can be addressed directly and indirectly
Memory that can be addressed indirectly
Size (bytes)
128
256
相關(guān)PDF資料
PDF描述
P89LPC922 MINIATURE POWER RELAY
P89LPC920 8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
P89LPC931 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
P8C15416Y-12 IC-8-BIT CMOS CPU
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P89LPC921FDH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
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