參數(shù)資料
型號(hào)： P89LPC903FD,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 35/53頁(yè)
文件大小： 0K
描述： IC 80C51 MCU FLASH 1K 8-SOIC
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 1
系列： LPC900
核心處理器： 8051
芯體尺寸： 8-位
速度： 7.3728MHz
連通性： UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LED，POR，WDT
輸入/輸出數(shù)： 6
程序存儲(chǔ)器容量： 1KB（1K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 剪切帶 (CT)
配用： 622-1006-ND - SOCKET ADAPTER BOARD
568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名稱(chēng)： 568-1996-1
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 17 December 2004
40 of 53
9397 750 14465
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.25 Additional features
8.25.1
Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor
completely, as if an external reset or Watchdog reset had occurred. Care should be
taken when writing to AUXR1 to avoid accidental software resets.
8.25.2
Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects
one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so
that the DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of inadvertently altering other
bits in the register.
8.26 Flash program memory
8.26.1
General description
The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and
programming. The Flash can be erased, read, and written as bytes. The Sector and
Page Erase functions can erase any Flash sector (256 bytes) or page (16 bytes). The
Chip Erase operation will erase the entire program memory. In-Circuit Programming
using standard commercial programmers is available. In addition, In-Application
Programming (IAP) and byte erase allows code memory to be used for non-volatile
data storage. On-chip erase and write timing generation contribute to a user-friendly
programming interface. The P89LPC901/902/903 Flash reliably stores memory
contents even after more than 100,000 erase and program cycles. The cell is
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 20. Watchdog timer in Watchdog mode (WDTE = ‘1’).
PRE2
PRE1
PRE0
–
WDRUN
WDTOF
WDCLK
WDCON (A7H)
CONTROL REGISTER
PRESCALER
002aaa423
SHADOW
REGISTER
FOR WDCON
8-BIT DOWN
COUNTER
WDL (C1H)
Watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
RESET
see note (1)
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