參數(shù)資料
型號： P89C669
廠商： NXP Semiconductors N.V.
英文描述： 80C51 8-bit microcontroller family with extended memory 96 kB Flash with 2 kB RAM
中文描述： 80C51的8位擴展內(nèi)存，2 KB RAM內(nèi)存96 kB閃存微控制器系列
文件頁數(shù)： 18/33頁
文件大?。?/td> 827K
代理商： P89C669
Philips Semiconductors
P89C669
80C51 8-bit microcontroller family with extended memory
Product data
Rev. 02 — 13 November 2003
18 of 33
9397 750 12299
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.
Static characteristics
[1]
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), 5 V, unless otherwise stated.
Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
OL
of ALE and ports 1, 3 and 4. The noise is
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus
operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be
desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
OL
can exceed these
conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
Capacitive loading on ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the V
DD
0.7 V specification when
the address bits are stabilizing.
Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from ‘1’ to ‘0’. The transition current reaches
its maximum value when V
IN
is approximately 2 V for 4.5 V < V
DD
< 5.5 V.
See
Figure 10
through
Figure 13
for I
CC
test conditions. f
osc
is the oscillator frequency in MHz.
This value applies to T
amb
= 0
°
C to +70
°
C.
Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
a) Maximum I
OL
per port pin: 15 mA
b) Maximum I
OL
per 8-bit port: 26 mA
[3]
[4]
[5]
[6]
[7]
[8]
Table 8:
T
amb
= 0
°
C to
+
70
°
C for commercial, unless otherwise specified; V
DD
= 4.5 V to 5.5 V unless otherwise specified.
Symbol Parameter
Conditions
V
IL
LOW-level input voltage
V
IH
HIGH-level input voltage
(ports 0, 1, 2, 3, 4, EA)
V
IH1
HIGH-level input voltage,
XTAL1, RST
V
OL
LOW-level output voltage,
ports 1, 2, 3, 4
[8]
V
OL1
LOW-level output voltage,
port 0, ALE, PSEN
[7][8]
V
OH
HIGH-level output voltage,
ports 1, 2, 3, 4
V
OH1
HIGH-level output voltage
(port 0 in external bus
mode), ALE
[9]
, PSEN
[3]
I
IL
Logical 0 input current,
ports 1, 2, 3, 4
I
TL
Logical 1-to-0 transition
current, ports 1, 2, 3, 4
[8]
V
IN
= 2.0 V
I
L1
Input leakage current, port 0
0.45 < V
IN
< V
DD
0.3
I
CC
Power supply current
Active mode
[5]
V
DD
= 5.5 V
Idle mode
[5]
Power-down mode or clock
stopped (see
Figure 13
for
conditions)
R
RST
Internal reset pull-down
resistor
C
10
Pin capacitance
[10]
(except EA)
DC electrical characteristics
Min
0.5
0.2V
DD
+ 0.9
Typ
[1]
-
-
Max
0.2V
DD
0.1
V
DD
+ 0.5
Unit
V
V
0.7V
DD
-
V
DD
+ 0.5
V
V
DD
= 4.5 V; I
OL
= 1.6 mA
-
-
0.4
V
V
DD
= 4.5 V; I
OL
= 3.2 mA
-
-
0.4
V
V
DD
= 4.5 V; I
OH
=
30 A
V
DD
0.7
-
-
V
V
DD
= 4.5 V;
I
OH
=
3.2 mA
V
DD
0.7
-
-
V
V
IN
= 0.4 V
1
-
75
μ
A
4.5 V < V
DD
< 5.5 V;
[4]
-
-
650
μ
A
-
-
-
-
-
-
-
-
-
20
±
10
-
7 + 2.7
×
f
osc
[MHz]
4 + 1.3
×
f
osc
[MHz]
100
μ
A
[5]
mA
mA
μ
A
40
-
225
k
-
-
15
pF
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