參數(shù)資料
型號(hào): P89C660
廠商: NXP Semiconductors N.V.
元件分類(lèi): 8位微控制器
英文描述: 80C51 8-bit Flash microcontroller family
中文描述: 80C51的8位閃存微控制器系列
文件頁(yè)數(shù): 78/89頁(yè)
文件大?。?/td> 491K
代理商: P89C660
Philips Semiconductors
Product data
P89C660/P89C662/P89C664/
P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
2002 Oct 28
78
AC ELECTRICAL CHARACTERISTICS (6 CLOCK MODE)
(Continued)
T
amb
= 0
°
C to +70
°
C, V
CC
= 5 V
±
10% or –40
°
C to +85
°
C,V
CC
= 5 V
±
5%, V
SS
= 0 V
1, 2
SYMBOL
PARAMETER
INPUT
OUTPUT
I
2
C Interface
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
NOTES:
1. Parameters are valid over operating temperature range and voltage range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. These values are characterized but not 100% production tested.
4. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
5. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1
μ
s.
6. Spikes on the SDA and SCL lines with a duration of less than 3 t
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
7. t
CLCL
= 1/f
OSC
= one oscillator clock period at pin XTAL1.
START condition hold time
7 t
CLCL
8 t
CLCL
7 t
CLCL
1
μ
s
0.3
μ
s
250 ns
250 ns
250 ns
0 ns
7 t
CLCL
4
7 t
CLCL
4
7 t
CLCL
4
1
μ
s
7
300 ns
7
> 4.0
μ
s
4
> 4.7
μ
s
46
> 4.0
μ
s
4
5
< 0.3
μ
s
6
> 10 t
CLCL
– t
RD
> 1
μ
s
4
> 4 t
CLCL
> 4 t
CLCL
– t
FC
> 4.7
μ
s
4
> 4.0
μ
s
4
> 4.7
μ
s
4
5
< 0.3
μ
s
6
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
SDA set-up time (before rep. START cond.)
SDA set-up time (before STOP cond.)
Data hold time
Repeated START set-up time
STOP condition set-up time
Bus free time
SDA rise time
SDA fall time
相關(guān)PDF資料
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P89C660HBA 80C51 8-bit Flash microcontroller family
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