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參數(shù)資料
| 型號： | P89C58X2BBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit Flash microcontroller family |
| 中文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 X 1.40 MM, LQFP-44 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 212K |
| 代理商： | P89C58X2BBD |
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Philips Semiconductors
Product specification
89C51/89C52/89C54/89C58
80C51 8-bit microcontroller family
4K/8K/16K/32K Flash
1999 Oct 27
22
AC ELECTRICAL CHARACTERISTICS
T
amb
= 0
°
C to +70
°
C or –40
°
C to +85
°
C, V
CC
= 5 V
±
10%, V
SS
= 0V
1, 2, 3
VARIABLE CLOCK
4
33MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
14
Oscillator frequency
Speed versions:
ALE pulse width
I;J;U (33 MHz)
3.5
33
3.5
21
33
MHz
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
14
2t
CLCL
–40
t
CLCL
–25
t
CLCL
–25
ns
14
Address valid to ALE low
5
ns
14
Address hold after ALE low
5
ns
14
ALE low to valid instruction in
4t
CLCL
–65
55
ns
14
ALE low to PSEN low
t
CLCL
–25
3t
CLCL
–45
5
ns
14
PSEN pulse width
45
ns
14
PSEN low to valid instruction in
3t
CLCL
–60
30
ns
14
Input instruction hold after PSEN
0
0
ns
14
Input instruction float after PSEN
t
CLCL
–25
5t
CLCL
–80
10
5
ns
14
Address to valid instruction in
70
ns
14
PSEN low to address float
10
ns
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
WHQX
t
QVWH
t
RLAZ
t
WHLH
External Clock
15, 16
RD pulse width
6t
CLCL
–100
6t
CLCL
–100
82
ns
15, 16
WR pulse width
82
ns
15, 16
RD low to valid data in
5t
CLCL
–90
60
ns
15, 16
Data hold after RD
0
0
ns
15, 16
Data float after RD
2t
CLCL
–28
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
32
ns
15, 16
ALE low to valid data in
90
ns
15, 16
Address to valid data in
105
ns
15, 16
ALE low to RD or WR low
3t
CLCL
–50
4t
CLCL
–75
t
CLCL
–30
t
CLCL
–25
7t
CLCL
–130
40
140
ns
15, 16
Address valid to WR low or RD low
45
ns
15, 16
Data valid to WR transition
0
ns
15, 16
Data hold after WR
5
ns
16
Data valid to WR high
80
ns
15, 16
RD low to address float
0
0
ns
15, 16
RD or WR high to ALE high
t
CLCL
–25
t
CLCL
+25
5
55
ns
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Shift Register
18
High time
17
t
CLCL
–t
CLCX
t
CLCL
–t
CHCX
5
ns
18
Low time
17
ns
18
Rise time
ns
18
Fall time
5
ns
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
4. Parts are guaranteed to operate down to 0 Hz.
17
Serial port clock cycle time
12t
CLCL
10t
CLCL
–133
2t
CLCL
–80
0
360
ns
17
Output data setup to clock rising edge
167
ns
17
Output data hold after clock rising edge
50
ns
17
Input data hold after clock rising edge
0
ns
17
Clock rising edge to input data valid
10t
CLCL
–133
167
ns
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