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| 型號(hào)： | P89C557E6 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Single-chip 8-bit microcontroller(單片8位微控制器) |
| 中文描述： | 單芯片8位微控制器（單片8位微控制器） |
| 文件頁(yè)數(shù)： | 32/64頁(yè) |
| 文件大?。?/td> | 476K |
| 代理商： | P89C557E6 |
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Philips Semiconductors
Product specification
P83C557E6/P80C557E6
Single-chip 8-bit microcontroller
1999 Mar 02
32
When SIO1 is in a master mode serial clock frequency is
determined by the clock rate bits CR2, CR1 and CR0. The various
bit rates are shown in Table 25.
The data shown in Table 25 do not apply to SIO1 in a slave mode. In
the slave modes, SIO1 will automatically synchronize with any clock
frequency up to 400kHz.
Table 25.
Selection of I
2
C-bus bit rate
BIT RATE (kHz) at f
CLK
CR2
CR1
CR0
12MHz
16MHz
1
0
0
50
66.7
1
0
1
3.75
5
1
1
0
75
100
1
1
1
100
200
1)
–
0
0
0
266.7
1)
0
0
1
7.5
300
1)
400
1)
10
0
1
0
400
1)
0
1
1
–
NOTE:
1. These bit rates are for “fast–mode” I
2
C bus applications and cannot be used for bit rates up to 100 kbit/sec.
Serial status register S1STA
S1STA is a read only register.
The contents of the status register may be used as a vector to a
service routine. This optimizes the response time of the software
and consequently that of the I
2
C–bus.
Figure 31. Serial status (S1STA) register.
7
6
5
4
3
2
1
0
S1STA (D9H)
SC4
SC3
SC2
SC1
SC0
0
0
0
Table 26.
Description of S1STA bits
BIT
FUNCTION
S1STA.7 to 3
5–bit status code
S1STA.2 to 0
These bits are held LOW (for service routine vector increment 8)
The following is a list of the status codes:
Table 27.
MST/TRX mode
S1STA VALUE
DESCRIPTION
08H
A START condition has been transmitted
10H
A repeated START condition has been transmitted
18H
SLA and W have been transmitted, ACK has been received
20H
SLA and W have been transmitted, ACK received
28H
DATA and S1DAT has been transmitted, ACK received
30H
DATA and S1DAT has been transmitted, ACK received
38H
Arbitration lost in SLA, R/W or DATA
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