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參數(shù)資料
| 型號： | P87C766CBP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for PAL/SECAM TV with OSD and VST |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 28/92頁 |
| 文件大小： | 382K |
| 代理商： | P87C766CBP |
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1999 Mar 10
28
Philips Semiconductors
Product specification
Microcontrollers for PAL/SECAM TV
with OSD and VST
P8xCx66 family
11.9
Interrupt Request Flag Register (IRQ1)
Bits IQ9 and IQ6 to IQ2 will be set to a logic 1, if one of the two conditions specified below is met:
If its associated port line is programmed to generate an interrupt when HIGH (selected using the Interrupt Polarity
Register) and the state of that port line is HIGH
If its associated port line is programmed to generate an interrupt when LOW (selected using the Interrupt Polarity
Register) and the state of that port line is LOW.
IQ7 is set to a logic 1, if the interrupt condition is met within the corresponding derivative function. Therefore, all IRQ1 bits
serve not only as pending interrupt request bits but also as interrupt status bits. This means that even if the external
interrupts are disabled (using the Interrupt Enable Register 1) the IRQ1 bits can still be set to a logic 1 if the interrupt
condition is met within the corresponding derivative function. For example, if the interrupt condition within VSYNC is met
then:
If IEN0.7 = X, IEN1.5 = 0 then IRQ1.5 = 1, no pending interrupt to CPU
If IEN0.7 = 0, IEN1.5 = 1 then IRQ1.5 = 1, interrupt to CPU is pending
If IEN0.7 = 1, IEN1.5 = 1 then IRQ1.5 = 1, interrupt will be serviced when either:
– The CPU finishes current instruction, if not in the interrupt service routine
– The current interrupt service routine is interrupted if the VSYNC has a higher interrupt priority
– This VSYNC interrupt becomes pending, waiting until the current higher priority level interrupt is serviced.
Bits IQ9 and IQ7 to IQ2 can be reset by software.
Table 31
Interrupt Request Flag Register (SFR address C0H)
Table 32
Description of IRQ1 bits
7
6
5
4
3
2
1
0
IQ9
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
IQ9
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
external interrupt 9 request flag (P1.7 port line)
reserved
external interrupt 7 request flag (VSYNC interrupt)
external interrupt 6 request flag (P1.4 port line)
external interrupt 5 request flag (P1.3 port line)
external interrupt 4 request flag (P1.2 port line)
external interrupt 3 request flag (P1.1 port line)
external interrupt 2 request flag (P1.0 port line)
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