參數(shù)資料
型號： P87C52X2FN,112
廠商： NXP Semiconductors
文件頁數(shù)： 28/62頁
文件大小： 0K
描述： IC 80C51 MCU 256 RAM 40DIP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 9
系列： 87C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
其它名稱： 568-7912-5
568-7912-5-ND
568-8361-5
935269602112
P87C52X2FN
P87C52X2FN,112-ND
P87C52X2FN-ND
Philips Semiconductors
Product data
P80C3xX2; P80C5xX2;
P87C5xX2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
2003 Jan 24
34
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL
FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
—
Not implemented. Reserved for future use.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU01522
ET0
EX1
ET1
ES
ET2
—
EA
0
1
2
3
4
5
6
7
IE
Address = 0A8H
Bit Addressable
Reset Value = 0X000000B
Figure 22. Interrupt Enable (IE) Register
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL
FUNCTION
IP.7
—
Not implemented, reserved for future use.
IP.6
—
Not implemented, reserved for future use.
IP.5
PT2
Timer 2 interrupt priority bit.
IP.4
PS
Serial Port interrupt priority bit.
IP.3
PT1
Timer 1 interrupt priority bit.
IP.2
PX1
External interrupt 1 priority bit.
IP.1
PT0
Timer 0 interrupt priority bit.
IP.0
PX0
External interrupt 0 priority bit.
SU01523
PT0
PX1
PT1
PS
PT2
—
0
1
2
3
4
5
6
7
IP
Address = 0B8H
Bit Addressable
Reset Value = xx000000B
Figure 23. Interrupt Priority (IP) Register
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
SYMBOL
FUNCTION
IPH.7
—
Not implemented, reserved for future use.
IPH.6
—
Not implemented, reserved for future use.
IPH.5
PT2H
Timer 2 interrupt priority bit high.
IPH.4
PSH
Serial Port interrupt priority bit high.
IPH.3
PT1H
Timer 1 interrupt priority bit high.
IPH.2
PX1H
External interrupt 1 priority bit high.
IPH.1
PT0H
Timer 0 interrupt priority bit high.
IPH.0
PX0H
External interrupt 0 priority bit high.
SU01524
PT0H
PX1H
PT1H
PSH
PT2H
—
0
1
2
3
4
5
6
7
IPH
Address = B7H
Bit Addressable
Reset Value = xx000000B
Figure 24. Interrupt Priority HIGH (IPH) Register
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