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參數(shù)資料
| 型號： | P83C270AAR |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| 中文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 文件頁數(shù)： | 25/80頁 |
| 文件大小： | 266K |
| 代理商： | P83C270AAR |
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1999 Jun 11
25
Philips Semiconductors
Product specification
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
P8xCx70 family
11.5
Busy interrupt and Watchdog Timer control
11.5.1
BUSY
INTERRUPT AND
W
ATCHDOG
C
ONTROL
R
EGISTER
(BWC)
The BUSY signal can generate an interrupt (PX7) to the CPU if enabled by IEN1.5, the vector address is 0063H. This
register is used to enable/disable the BUSY interrupt and the Watchdog Timer.
Table 32
BUSY interrupt and Watchdog Control Register (SFR address EBH)
Table 33
Description of the BWC bits
11.5.2
I
NTERRUPT
R
EQUEST
(RBUSY)
RBUSY is bit 5 of the SFR IRQ1 (address 98H). A falling edge of the active BUSY signal generates a pending interrupt
to the CPU and forces the RBUSY bit HIGH. In the service routine, this bit should be cleared before returning to the main
routine. As long as RBUSY is HIGH, a pending interrupt is always present. Each time BUSY is activated by a falling edge,
the RBUSY is set HIGH. If the interrupt is not served by the next falling BUSY edge, then RBUSY is written to HIGH again
and no error of overrun is indicated.
7
6
5
4
3
2
1
0
EW
BUSY
BIT
SYMBOL
EW
DESCRIPTION
7 to 2
1
These 6 bits are not used.
Enable Watchdog Timer.
If EW = 0, then the Watchdog Timer is disabled. If EW = 1,
then the Watchdog Timer is enabled and the Power-down mode is disabled.
When BUSY = 0, an active external interrupt will generate an interrupt to the CPU.
When BUSY = 1, external interrupts are disabled.
0
BUSY
It is not recommended to update the display RAM when the BUSY signal is active
(LOW), due to the effect it may have on the OSD display. The display RAM can be
updated when the BUSY signal is inactive.
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