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參數(shù)資料
| 型號： | P80C52SBAA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, MO-047, SOT187-2, LCC-44 |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 337K |
| 代理商： | P80C52SBAA |
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Philips Semiconductors
Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
1999 Apr 01
34
(8XC51RX+ ONLY)
ERAM
256 BYTES
UPPER
128 BYTES
INTERNAL RAM
LOWER
128 BYTES
INTERNAL RAM
SPECIAL
FUNCTION
REGISTER
ééééé
ééééé
ééééé
ééééé
ééééé
2FF
(RD TO RD+)
FF
00
FF
00
FF
00
80
80
EXTERNAL
DATA
MEMORY
FFFF
0000
0100
300 (RD+ only)
SU00834
Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR 89C51RC+/RD+)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH
and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except
through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output reset HIGH pulse at the
RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to
the WDTRST, SFR location 0A6H. When WDT is enabled, the user
needs to service it by writing to 01EH and 0E1H to WDTRST to
avoid WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When using the WDT,
a 1Kohm resistor must be inserted between RST of the device and
the Power On Reset circuitry. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This
means the user must reset the WDT at least every 16383 machine
cycles. To reset the WDT, the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the reset pin. The RESET pulse duration is
98
×
T
OSC
, where T
OSC
= 1/f
OSC
. To make the best use of the WDT,
it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
In applications using the Hardware Watchdog Timer of the
P8xC51RD+, a series resistor (1K
between the reset pin and any external components. Without this
resistor the watchdog timer will not function.
20%) needs to be included
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