參數(shù)資料
型號(hào)： P80C528
廠商： NXP Semiconductors N.V.
英文描述： 8-bit microcontrollers
中文描述： 8位微控制器
文件頁(yè)數(shù)： 15/26頁(yè)
文件大?。?/td> 447K
代理商： P80C528
Philips Semiconductors
Product specification
80C528/83C528
CMOS single-chip 8-bit microcontrollers
1995 Feb 02
15
AC ELECTRICAL CHARACTERISTICS – I
2
C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
I
2
C SPECIFICATION
SCL TIMING CHARACTERISTICS
t
HD;STA
START condition hold time
≥
14 t
CLCL1
Note 2
≥
4.0
μ
s
t
LOW
SCL LOW time
≥
16 t
CLCL
≥
14 t
CLCL1
≤
1
μ
s
4
Note 2
≥
4.7
μ
s
t
HIGH
SCL HIGH time
≥
80 t
CLCL3
≥
4.0
μ
s
t
RC
SCL rise time
Note 5
≤
1.0
μ
s
t
FC
SCL fall time
≤
0.3
μ
s
4
≤
0.3
μ
s
6
≤
0.3
μ
s
SDA TIMING CHARACTERISTICS
t
SU;DAT1
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
NOTES:
1. At f
= 3.5MHz, this evaluates to 14
×
286ns = 4
μ
s, i.e., the bit-level I
2
C interface can respond to the I
2
C protocol for f
CLK
≥
3.5MHz.
2. This parameter is determined by the user software, it has to comply with the I
2
C.
3. This value gives the autoclock pulse length which meets the I
2
C specification for the specified XTAL clock frequency range. Alternatively, the
SCL pulse may be timed by software.
4. Spikes on SDA and SCL lines with a duration of less than 4
×
f
CLK
will be filtered out.
5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be
≤
1
μ
s.
6. The maximum capacitance on bus lines SDA and SCL is 400pF.
Data set-up time
≥
250ns
≥
0ns
≥
14 t
CLCL1
≥
14 t
CLCL1
≥
14 t
CLCL1
≤
1
μ
s
4
≤
0.3
μ
s
4
Note 2
≥
250ns
≥
0ns
≥
4.7
μ
s
≥
4.0
μ
s
≥
4.7
μ
s
≤
1.0
μ
s
≤
0.3
μ
s
Data hold time
Note 2
Repeated START set-up time
Note 2
STOP condition set-up time
Note 2
Bus free time
Note 2
SDA rise time
Note 5
≤
0.3
μ
s
6
SDA fall time
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