參數(shù)資料
型號： P80C32UFAA,512
廠商： NXP Semiconductors
文件頁數(shù)： 9/32頁
文件大小： 0K
描述： IC 80C51 MCU 8BIT ROMLESS 44PLCC
產(chǎn)品培訓模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標準包裝： 26
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲器類型： ROMless
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
產(chǎn)品目錄頁面： 705 (CN2011-ZH PDF)
其它名稱： 568-3195-5
935260357512
P80C32UFAA
Philips Semiconductors
Product specification
80C31/80C32
80C51 8-bit microcontroller family
128/256 byte RAM ROMless low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
2000 Aug 07
17
Interrupt Priority Structure
The 80C31 and 80C32 have a 6-source four-level interrupt
structure. They are the IE, IP and IPH. (See Figures 10, 11, and 12.)
The IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
INTERRUPT PRIORITY LEVEL
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
Level 3 (highest priority)
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
X0
1
IE0
N (L)1
Y (T)2
03H
T0
2
TP0
Y
0BH
X1
3
IE1
N (L)
Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
RI, TI
N
23H
T2
6
TF2, EXF2
N
2BH
NOTES:
1. L = Level activated
2. T = Transition activated
EX0
IE (0A8H)
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL
FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
—
Not implemented. Reserved for future use.
IE.5
ET2
Timer 2 interrupt enable bit.
IE.4
ES
Serial Port interrupt enable bit.
IE.3
ET1
Timer 1 interrupt enable bit.
IE.2
EX1
External interrupt 1 enable bit.
IE.1
ET0
Timer 0 interrupt enable bit.
IE.0
EX0
External interrupt 0 enable bit.
SU00571
ET0
EX1
ET1
ES
ET2
—
EA
0
1
2
3
4
5
6
7
Figure 10. IE Registers
相關(guān)PDF資料
PDF描述
MC68HC908KX8CP IC MCU 8MHZ 8K FLASH 16-DIP
MC68HC908KX8CDW IC MCU 8MHZ 8K FLASH 16-SOIC
MC68HC908JB8ADW IC MCU 3MHZ 8K FLASH 28-SOIC
MC68HC908JL3CP IC MCU 8MHZ 4K FLASH 28-DIP
MC68HC908JL3CDW IC MCU 8MHZ 4K FLASH 28-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P80C32UFAA-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P80C32UFBB 制造商:NXP Semiconductors 功能描述:MCU 8-bit MCS51 8051 CISC ROMLess 5V 44-Pin PQFP
P80C32UFBB,557 功能描述:8位微控制器 -MCU 80C51 256B 33MHZ ROMLESS RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
P80C32UFBB-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
P80C32UFPN 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit CMOS (low voltage, low power and high speed) microcontroller families
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*