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參數(shù)資料
| 型號： | P75N02LD |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| 中文描述： | N溝道增強(qiáng)模式的邏輯電平場效應(yīng)晶體管 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 122K |
| 代理商： | P75N02LD |
1
AUG-02-2001
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LD
TO-252 (D
2
PAK)
NIKO-SEM
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
UNITS
Gate-Source Voltage
V
GS
±20
V
T
C
= 25 °C
75
Continuous Drain Current
T
C
= 100 °C
I
D
50
Pulsed Drain Current
1
I
DM
170
Avalanche Current
I
AR
60
A
Avalanche Energy
L = 0.1mH
E
AS
140
Repetitive Avalanche Energy
2
L = 0.05mH
E
AR
5.6
mJ
T
C
= 25 °C
65
Power Dissipation
T
C
= 100 °C
P
D
38
W
Operating Junction & Storage Temperature Range
T
j
, T
stg
-55 to 150
Lead Temperature (
1
/
16
” from case for 10 sec.)
T
L
275
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
MAXIMUM
UNITS
Junction-to-Case
R
θ
JC
2.3
Junction-to-Ambient
R
θ
JA
62.5
Case-to-Heatsink
R
θ
CS
0.6
°C / W
1
Pulse width limited by maximum junction temperature.
2
Duty cycle
≤
1
％
ELECTRICAL CHARACTERISTICS (T
C
= 25 °C, Unless Otherwise Noted)
LIMITS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
UNIT
STATIC
Drain-Source Breakdown Voltage
V
(BR)DSS
V
GS
= 0V, I
D
= 250
μ
A
25
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= 250
μ
A
1
1.5
3
V
Gate-Body Leakage
I
GSS
V
DS
= 0V, V
GS
= ±20V
±250
nA
V
DS
= 20V, V
GS
= 0V
25
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 20V, V
GS
= 0V, T
J
= 125 °C
250
μ
A
1. GATE
2. DRAIN
3. SOURCE
PRODUCT SUMMARY
V
(BR)DSS
R
DS(ON)
I
D
25
5m
Ω
75A
G
D
S
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