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參數資料
| 型號： | P4C189-35PC |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 16 x 4 STATIC CMOS RAM WITH INVERTING OUTPUTS |
| 中文描述： | 16 X 4 STANDARD SRAM, 35 ns, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 178K |
| 代理商： | P4C189-35PC |
P4C189
Page 3 of 8
Document #
SRAM100
Rev OR
addressed word is read out on the inverting outputs (
O
0
through
O
). The outputs of the memory go to an inactive
high impedance state whenever chip select (
CS
) is HIGH,
or during the write operation when write enable (
WE
) is
LOW.
An active LOW write enable (
WE
) controls the writing/
reading operation of the memory. When chip select (
CS
)
and write enable (
WE
) are LOW, the information on data
inputs (D
through D
) is written into the addressed memory
word. Reading is performed with chip select (
CS
) LOW and
write enable (
WE
) HIGH. The information stored in the
FUNCTIONAL DESCRIPTION
Notes:
H = HIGH
L = Low
X = Don't Care
HIGH Z = Implies outputs are disabled or off. This condition
is defined as high impedance state.
Mode
CS
WE
Output
Standby
H
X
High Z
Read
L
H
D
OUT
High Z
Write
L
L
TRUTH TABLE
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
Read Cycle Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
-35
Unit
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Min
35
2
2
Max
35
15
10
Parameter
Address Access Time
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