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參數(shù)資料
| 型號： | P4C188-15LMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 中文描述： | 16K X 4 STANDARD SRAM, 15 ns, CQCC22 |
| 封裝： | 0.290 X 0.490 INCH, CERAMIC, LCC-22 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 215K |
| 代理商： | P4C188-15LMB |
P4C188/188L
Page 4 of 12
Document #
SRAM112
REV A
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
-10
Min
10
2
2
0
Max
10
10
5
10
-12
Min
12
2
2
0
Max
12
12
6
12
-15
Min
15
2
2
0
Max
15
15
6
15
-20
Min
20
2
3
0
Max
20
20
8
20
-25
Min
25
2
3
0
Max
25
25
10
25
-35
Min
35
2
3
0
Max
35
35
20
35
-45
Min
45
2
3
0
Max
45
45
25
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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PDF描述 |
|---|---|
| P4C188-15PM | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| P4C188-15PMB | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| P4C188-35LI | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| P4C188-35LMB | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| P4C188-35PM | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
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