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參數(shù)資料
| 型號(hào)： | P4C187-45DI |
| 廠商： | Pyramid Semiconductor Corporation |
| 英文描述： | ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS |
| 中文描述： | 超高速64K的× 1靜態(tài)CMOS五羊 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 323K |
| 代理商： | P4C187-45DI |
P4C187/187L
Page 4 of 12
Document #
SRAM111
REV B
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t
RC
Read Cycle Time
10
12
15
20
25
35
45
55
70
85
t
AA
Address Access Time
10
12
15
20
25
35
45
55
70
85
t
AC
Chip Enable Access Time
10
12
15
20
25
35
45
65
70
85
t
OH
Output Hold from Address Change
2
2
2
2
2
2
2
2
2
2
t
LZ
Chip Enable to Output in Low Z
2
2
2
2
2
2
2
2
2
2
t
HZ
Chip Disable to Output in High Z
5
6
8
10
12
17
20
25
30
35
t
PU
Chip Enable to Power Up Time
0
0
0
0
0
0
0
0
0
0
t
PD
Chip Disable to Power Down Time
10
12
15
20
25
35
45
55
70
85
Parameter
Symbol
-10
-12
-45
-55
-70
-85
-15
-20
-25
-35
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