參數(shù)資料
型號(hào): P4C187-35CI
廠商: Pyramid Semiconductor Corporation
英文描述: ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
中文描述: 超高速64K的× 1靜態(tài)CMOS五羊
文件頁(yè)數(shù): 5/12頁(yè)
文件大小: 323K
代理商: P4C187-35CI
P4C187/187L
Page 5 of 12
Document #
SRAM111
REV B
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED)
(9)
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t
WC
Write Cycle Time
10
12
15
20
25
35
45
55
70
85
t
CW
Chip Enable Time to
End of Write
Address Valid to End
of Write
8
10
12
15
20
25
30
35
40
45
t
AW
8
10
12
15
20
25
30
35
40
45
t
AS
Address Set-up Time
0
0
0
0
0
0
0
0
0
0
t
WP
Write Pulse Width
8
10
12
15
20
25
30
35
40
45
t
AH
Address Hold Time
from End of Write
Data Valid to End of
Write
0
0
0
0
0
0
0
0
0
0
t
DW
6
7
10
13
15
20
25
30
35
40
t
DH
Data Hold Time
0
0
0
0
0
0
0
0
0
0
t
WZ
Write Enable to
Output in High Z
Output Active from
End of Write
6
7
8
12
15
17
20
25
30
35
t
OW
0
0
0
0
0
0
0
0
0
0
-15
-20
-25
-35
-45
-55
-70
-85
Parameter
Symbol
-10
-12
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