參數(shù)資料
型號(hào): P4C170-55CM
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
中文描述: 4K X 4 STANDARD SRAM, 55 ns, CDIP20
封裝: 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-20
文件頁(yè)數(shù): 4/15頁(yè)
文件大?。?/td> 246K
代理商: P4C170-55CM
P4C168, P4C169, P4C170
Page 4 of 15
Document #
SRAM107
REV A
Notes:
7. ADDRESS must be valid prior to, or coincident with
CE
/
CS
transition
low. For Fast
CS
, t
must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2 (
CE
/
CS
CONTROLLED)
(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (
OE
CONTROLLED)
(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)
(5,6)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
/
CS
and
OE
are LOW for READ cycle.
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