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參數(shù)資料
| 型號： | P4C170-35CM |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS |
| 中文描述： | 4K X 4 STANDARD SRAM, 35 ns, CDIP20 |
| 封裝： | 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-20 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 246K |
| 代理商： | P4C170-35CM |
P4C168, P4C169, P4C170
Page 7 of 15
Document #
SRAM107
REV A
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long high-
inductance leads that cause supply bounce must be avoided by bringing
the V
and ground planes directly up to the contactor fingers. A high
frequency capacitor of 0.01 μF is also required between V
CC
and ground.
Figure 1. Output Load
Figure 2. Thevenin Equivalent
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
To avoid signal reflections, proper termination must be used; for
example, a 50
test environment should be terminated into a 50
load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116
resistor must be used in series with D
OUT
to match 166
(Thevenin
Resistance).
LCC PIN CONFIGURATION
LCC (L9)
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