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參數(shù)資料
| 型號： | P4C147-25LSM |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM |
| 中文描述： | 4K X 1 STANDARD SRAM, 25 ns, CQCC18 |
| 封裝： | 0.295 X 0.335 INCH, CERAMIC, LCC-18 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 200K |
| 代理商： | P4C147-25LSM |
P4C147
Page 4 of 10
Document #
SRAM103
REV A
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
high, the output remains
in a high impedance state.
-10
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED)
(9)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CONTROLLED)
(9)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from
End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
Min
10
8
8
0
8
0
5
0
0
Max
5
-12
Min
12
10
10
0
10
0
6
0
0
Max
6
-15
Min
15
12
12
0
12
0
7
0
0
Max
7
-20
Min
20
15
15
0
14
0
9
0
0
Max
9
-25
Min
25
20
20
0
15
0
12
0
0
Max
12
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
-35
Min
35
25
25
0
18
0
15
0
0
Max
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
11. Write Cycle Time is measured from the last valid address to the first
transition address.
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