參數(shù)資料
型號(hào): P4C1298-35PM
廠商: Pyramid Semiconductor Corporation
英文描述: ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
中文描述: 超高速64K的× 4靜態(tài)CMOS存儲(chǔ)器
文件頁(yè)數(shù): 6/11頁(yè)
文件大小: 135K
代理商: P4C1298-35PM
P4C1298/L
Page 6 of 11
Document #
SRAM135
REV OR
12. Write Cycle Time is measured from the last valid address to the first
transition address.
13. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10.
OE
is LOW for this WRITE cycle.
11. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED)
(9)
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Min
15
Max
Min
20
Max
Min
25
Max
Min
35
Max
Min
45
Max
t
WC
Write Cycle Time
t
CW
Chip Enable Time to End of Write
10
15
20
25
30
t
AW
Address Valid to End of Write
10
15
20
25
30
t
AS
Address Set-up Time
0
0
0
0
0
t
WP
Write Pulse Width
10
15
20
25
30
t
AH
Address Hold Time from End of Write
0
0
0
0
0
t
DW
Data Valid to End of Write
9
10
15
20
20
t
DH
Data Hold Time
0
0
0
0
0
t
WZ
Write Enable to Output in High Z
7
10
15
20
20
t
OW
Output Active from End of Write
0
0
0
0
0
Sym
Parameter
-45
-15
-20
-25
-35
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