參數(shù)資料
型號: P4C1256-35DMLF
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: HIGH SPEED 32K x 8 STATIC CMOS RAM
中文描述: 32K X 8 STANDARD SRAM, 35 ns, CDIP28
封裝: 0.600 INCH, ROHS COMPLIANT, CERAMIC, DIP-28
文件頁數(shù): 7/17頁
文件大?。?/td> 183K
代理商: P4C1256-35DMLF
P4C1256
Page 7 of 17
Document #
SRAM119
REV G
Notes:
10.
CE
and WE must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
and t
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CONTROLLED)
(10)
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