參數(shù)資料
型號(hào): P4C116-35CM
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS
中文描述: 2K X 8 STANDARD SRAM, 35 ns, CDIP24
封裝: 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-24
文件頁(yè)數(shù): 6/14頁(yè)
文件大?。?/td> 251K
代理商: P4C116-35CM
P4C116/P4C116L
Page 6 of 14
Document #
SRAM110
REV A
Mode
CE
OE
WE
I/O
Power
Standby
H
X
X
High Z
Standby
D
Disabled
L
H
H
High Z
Active
Read
L
L
H
D
OUT
High Z
Active
Write
L
X
L
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
TRUTH TABLE
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C116/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the V
and ground
planes directly up to the contactor fingers. A 0.01 μF high frequency
capacitor is also required between V
and ground. To avoid signal
reflections, proper termination must be used; for example, a 50
test
environment should be terminated into a 50
load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116
resistor must be used in
series with D
OUT
to match 166
(Thevenin Resistance).
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相關(guān)代理商/技術(shù)參數(shù)
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