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參數(shù)資料
| 型號： | P4C116-15LC |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS |
| 中文描述： | 2K X 8 STANDARD SRAM, 15 ns, QCC24 |
| 封裝： | 0.300 X 0.400 INCH, LCC-24 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 251K |
| 代理商： | P4C116-15LC |
P4C116/P4C116L
Page 4 of 14
Document #
SRAM110
REV A
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
and I
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
transition
TIMING WAVEFORM OF READ CYCLE NO. 1 (
OE
CONTROLLED)
(5)
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| P4C116-15PMB | 制造商:PYRAMID 制造商全稱:Pyramid Semiconductor Corporation 功能描述:ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS |
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