參數(shù)資料
型號: P4C1049L-55JMB
廠商: PYRAMID SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: HIGH SPEED 512K x 8 STATIC CMOS RAM
中文描述: 512K X 8 STANDARD SRAM, 55 ns, PDSO36
封裝: 0.400 INCH, SOJ-36
文件頁數(shù): 5/12頁
文件大?。?/td> 222K
代理商: P4C1049L-55JMB
P4C1049
Page 5 of 12
Document #
SRAM128
REV OR
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (
CE
CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
and I
not more negative than –2.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
transition LOW.
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