Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
372
Freescale Semiconductor
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
s
8.3.2.5
PWM Center Align Enable Register (PWMCAE)
ThePWMCAEregistercontainseightcontrolbitsfortheselectionofcenteralignedoutputsorleftaligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 8.4.2.5,“LeftAlignedOutputs”
and
Section 8.4.2.6,“CenterAlignedOutputs”
foramoredetailed
description of the PWM output modes.
Table 8-4. PWMPRCLK Field Descriptions
Field
Description
6–4
PCKB[2:0]
Prescaler Select for Clock B
— Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
7. These three bits determine the rate of clock B, as shown in
Table 8-5
.
2–0
PCKA[2:0]
Prescaler Select for Clock A
— Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
5. These three bits determine the rate of clock A, as shown in
Table 8-6
.
Table 8-5. Clock B Prescaler Selects
PCKB2
0
0
0
0
1
1
1
1
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
Table 8-6. Clock A Prescaler Selects
PCKA2
0
0
0
0
1
1
1
1
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
7
6
5
4
3
2
1
0
R
W
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
Reset
0
0
0
0
0
0
0
0
Figure 8-7. PWM Center Align Enable Register (PWMCAE)