![](http://datasheet.mmic.net.cn/370000/P312XDP512F0VFV_datasheet_16728159/P312XDP512F0VFV_371.png)
Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
371
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
8.3.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
Table 8-3. PWMCLK Field Descriptions
Field
Description
7
PCLK7
Pulse Width Channel 7 Clock Select
0 Clock B is the clock source for PWM channel 7.
1 Clock SB is the clock source for PWM channel 7.
6
PCLK6
Pulse Width Channel 6 Clock Select
0 Clock B is the clock source for PWM channel 6.
1 Clock SB is the clock source for PWM channel 6.
5
PCLK5
Pulse Width Channel 5 Clock Select
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
4
PCLK4
Pulse Width Channel 4 Clock Select
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
3
PCLK3
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
2
PCLK2
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
1
PCLK1
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
0
PCLK0
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
7
0
6
5
4
3
0
2
1
0
R
W
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-6. PWM Prescale Clock Select Register (PWMPRCLK)