Chapter 19 Debug (S12XDBGV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
706
Freescale Semiconductor
19.3.1.9
Debug State Control Register 2 (DBGSCR2)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state while in State2. The matches refer to the match channels of the comparator match
controllogicasdepictedin
Figure 19-1
anddescribedin
Section 19.3.1.11.1,“DebugComparatorControl
Register (DBGXCTL)”
. Comparators must be enabled by setting the comparator enable bit in the
associated DBGXCTL control register.
Table 19-21. State1 Sequencer Next Sate Selection
SC[3:0]
Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Any match triggers to state2
Any match triggers to state3
Any match triggers to final state
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
Match2 triggers to final state....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers to final state....... Other matches have no effect
Reserved
Reserved
Reserved
Reserved
0x0027
7
0
6
0
5
0
4
0
3
2
1
0
R
W
SC3
SC2
SC1
SC0
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 19-11. Debug State Control Register 2 (DBGSCR2)